Ratiometric clock systems for integrated receivers and associated methods

ABSTRACT

A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.

TECHNICAL FIELD OF THE INVENTION

This invention relates to receiver architectures for radio-frequencycommunications. More particularly, the present invention relates toclock systems for integrated receivers.

BACKGROUND

Radio frequency (RF) receivers are used in a wide variety ofapplications such as television, cellular telephones, pagers, globalpositioning system (GPS) receivers, cable modems, cordless phones,radios and other devices that receive RF signals. RF receivers typicallyrequire frequency translation or mixing. For example, with respect to FMaudio broadcasts, FM radio receivers may translate one broadcast channelin the FM frequency band to an intermediate frequency. Within the UnitedStates, FM radios will typically translate FM audio signals, which arebroadcast in 200 KHz channels in the frequency band from 88 MHz to 108MHz, to an intermediate frequency of 10.7 MHz. FM demodulators andstereo decoders can then convert this 10.7 MHz IF signal to demodulatedleft and right audio signal that can be sent to stereo speakers.Although other countries will have different frequency bands and channelspacing, the reception of audio broadcast signals, such as FM audiobroadcasts, is similarly accomplished using RF receivers.

The majority of typical RF receivers perform frequency translation ormixing using an oscillator and an analog multiplier or mixer. Anoscillator will typically output a local oscillator (LO) signal in theform of a sine wave or periodic wave having a tuned frequency (f_(LO)).A mixer then mixes the RF input signal spectrum, which includes desiredspectral content at a target channel having a particular centerfrequency (f_(CH)), with the LO signal to form an output signal havingspectral content at frequencies equal to the sum and difference of thetwo input frequencies, namely f_(CH)+f_(LO) and f_(CH)−f_(LO). One ofthese components forms the channel center frequency translated to thedesired IF frequency, and the other component can be filtered out. Theoscillator can be implemented with a variety of circuits, including, forexample, a tuned inductor-capacitor (LC) oscillator, a charge relaxationoscillator, or a ring oscillator.

Typical systems often include separate integrated circuits that oftenuse external clock signals of 10 MHz or above to drive digital signalprocessing circuitry utilized to process the received signals. Theseclock signals, however, would tend to cause significantperformance-degrading interference if an effort were made to integratethis digital circuitry on the same integrated circuit as the mixer andLO circuitry for an RF receiver.

SUMMARY OF THE INVENTION

The present invention is a ratiometric clock system for an integratedreceiver and associated method that provides an advantageous solutionfor combining digital signal processing circuitry on the same integratedcircuit as mixer and local oscillator circuitry.

In one embodiment, the present invention is an integrated receiver,including a mixer coupled to receive an RF signal spectrum and a mixingsignal as inputs and having a mixed signal as an output where the RFinput signal spectrum includes a plurality of channels, local oscillator(LO) generation circuitry coupled to receive a channel selection signalas an input and configured to provide an oscillation signal where theoscillation signal is dependent upon the channel selection signal andbeing used to generate the mixing signal for the mixer, conversioncircuitry coupled to receive the mixed signal from the mixer andconfigured to output a digital signal where the conversion circuitry isconfigured to utilize a digital clock signal, digital-signal-processor(DSP) circuitry coupled to receive the digital signal from theconversion circuitry and configured to output a digital audio signalwhere the DSP circuitry is configured to utilize the digital clocksignal, and a ratiometric clock system configured to generate the mixingsignal and the digital clock signal from the oscillation signal, whereinthe mixer, the LO generation circuitry, the conversion circuitry, andthe DSP circuitry are integrated within a single integrated circuit.

In another embodiment, the present invention is a ratiometric clocksystem for an integrated receiver, including local oscillator (LO)generation circuitry coupled to receive a channel selection signal as aninput and configured to provide an oscillation signal where theoscillation signal is dependent upon the channel selection signal, afirst divider coupled to receive the oscillation signal where the firstdivider is an output signal utilized to generate mixing signals for amixer integrated on an integrated circuit with the LO generationcircuitry, and a second divider coupled to receive the oscillationsignal where the second divider provides an output signal utilized togenerate clock signals for digital signal processing (DSP) circuitryintegrated on the integrated circuit with the LO generation circuitry.

In another embodiment, the present invention is a method for tuningchannels within a signal spectrum, including generating an oscillationsignal, the oscillation signal being dependent upon a channel selectionsignal, creating a mixing signal and a digital clock signal based uponthe oscillation signal such that the mixing signal and the digital clocksignal are ratiometric, mixing an RF input signal spectrum having aplurality of channels with the mixing signal to generate an outputsignal, converting the output signal to a digital signal, and processingthe digital signal to generate tuned digital output signals, wherein thedigital clock signal is utilized in the converting step, in theprocessing step, or in both the converting and the processing steps andwherein the generating, creating, mixing, converting and processingsteps are performed within a single integrated circuit.

DESCRIPTION OF THE DRAWINGS

It is noted that the appended drawings illustrate only exemplaryembodiments of the invention and are, therefore, not to be consideredlimiting of its scope, for the invention may admit to other equallyeffective embodiments.

FIG. 1A is a block diagram of an embodiment for an integratedterrestrial broadcast receiver that utilizes a low-IF architecture.

FIG. 1B is a more detailed block diagram for circuit blocks in FIG. 1A.

FIG. 1C is a block diagram of one example implementation for anintegrated terrestrial broadcast receiver including example externalcomponents.

FIG. 2A is a block diagram of an embodiment for an integratedterrestrial broadcast receiver that utilizes a phase lock loop (PLL) anda ratiometric clock to provide mixing signals and digital clock signalfor the receiver circuitry.

FIG. 2B is a block diagram for a ratiometric clock system.

FIG. 3A is a block diagram of an alternative embodiment for anintegrated terrestrial broadcast receiver that utilizes tuning controlcircuitry and a ratiometric clock to provide mixing signals and digitalclock signal for the receiver circuitry.

FIG. 3B is a block diagram of an alternative embodiment for anintegrated terrestrial broadcast receiver that utilizes a ratiometricdigital clock and an external reference clock for digital circuitry.

FIG. 4A is a block diagram of an embodiment for an integratedterrestrial broadcast receiver that includes both AM broadcast receptionand FM broadcast reception.

FIG. 4B is a block diagram of an embodiment for a portable device thattakes advantage of the integrated terrestrial broadcast receiver,according to the present invention.

FIG. 5A is a block diagram for an embodiment of an integratedterrestrial broadcast receiver that includes local oscillator (LO)control circuitry for adding certain frequency control features.

FIG. 5B is a signal diagram for one frequency control feature providedby the embodiment of FIG. 5A, namely high-side versus low-side localoscillator (LO) signal injection.

FIG. 5C is a signal diagram for another frequency control featureprovided by the embodiment of FIG. 5A, namely programmable intermediatefrequency (IF) locations.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is a ratiometric clock system for an integratedreceiver and associated method that provides an advantageous solutionfor combining digital signal processing circuitry on the same integratedcircuit as mixer and local oscillator circuitry.

FIG. 1A is a block diagram of an embodiment 100 for an integratedterrestrial broadcast receiver that utilizes a low-IF architecture. Theinput signal spectrum (f_(RF)) 112 is expected to be a radio frequency(RF) signal spectrum that includes a plurality of channels that can betuned. It is noted that as used herein, a “radio frequency” or RF signalmeans an electrical signal conveying useful information and having afrequency from about 3 kilohertz (kHz) to thousands of gigahertz (GHz),regardless of the medium through which such signal is conveyed. Thus anRF signal may be transmitted through air, free space, coaxial cable,fiber optic cable, etc. More particularly, the present invention canprovide an advantageous architecture for an FM terrestrial broadcastreceiver. For purposes of the description below, therefore, the RFsignal spectrum (f_(RF)) 112 will be discussed primarily with respect tothe RF signal spectrum (f_(RF)) 112 being an FM terrestrial broadcastspectrum that includes a plurality of different FM broadcasts channelscentered at different broadcast frequencies.

Looking back to the embodiment 100 in FIG. 1A, a low noise amplifier(LNA) 102 receives the RF signal spectrum (f_(RF)) 112. The output ofthe LNA 102 is then applied to mixer 104, and mixer 104 generates real(I) and imaginary (Q) output signals, as represented by signals 116. Togenerate these low-IF signals 116, the mixer 104 uses phase shiftedlocal oscillator (LO) mixing signals (f_(LO)) 118. The LO generationcircuitry 130 includes oscillation circuitry and outputs the twoout-of-phase LO mixing signals (f_(LO)) 118 that are used by the mixer104. The outputs of mixer 104 are at a low-IF, which can be designed tobe fixed or may be designed to vary, for example, if discrete steptuning is implemented for the LO generation circuitry 130. An example oflarge step LO generation circuitry that utilizes discrete tuning stepsis described in the co-owned and co-pending U.S. patent application Ser.No. 10/412,963, which was filed Apr. 14, 2003, which is entitled“RECEIVER ARCHITECTURES UTILIZING COARSE ANALOG TUNING AND ASSOCIATEDMETHODS,” and which is hereby incorporated by reference in its entirety

Low-IF conversion circuitry 106 receives the real (I) and imaginary (Q)signals 116 and outputs real and imaginary digital signals, asrepresented by signals 120. The low-If conversion circuitry 106preferably includes band-pass or low-pass analog-to-digital converter(ADC) circuitry that converts the low-IF input signals to the digitaldomain. And the low-If conversion circuitry 106 provides, in part,analog-to-digital conversion, signal gain and signal filteringfunctions. Further digital filtering and digital processing circuitrywith the digital signal processing (DSP) circuitry 108 is then used tofurther tune and extract the signal information from the digital signals120. The DSP circuitry 108 then produces baseband digital output signals122. When the input signals relate to FM broadcasts, this digitalprocessing provided by the DSP circuitry 108 can include, for example,FM demodulation and stereo decoding. And the digital output signals 122can be left (L) and right (R) digital audio output signals 122 thatrepresent the content of the FM broadcast channel being tuned, asdepicted in the embodiment 100 of FIG. 1A. It is noted that the outputof the receiver 100 can be other desired signals, including, forexample, low-IF quadrature I/Q signals from an analog-to-digitalconverter that are passed through a decimation filter, a baseband signalthat has not yet be demodulated, multiplexed L+R and L−R audio signals,L and R analog audio signals, and/or any other desired output signals.

It is noted that as used herein low-IF conversion circuitry refers tocircuitry that in part mixes the target channel within the input signalspectrum down to a fixed IF frequency, or down to a variable IFfrequency, that is equal to or below about three channel widths. Forexample, for FM broadcasts within the United States, the channel widthsare about 200 kHz. Thus, broadcast channels in the same broadcast areaare specified to be at least about 200 kHz apart. For the purposes ofthis description, therefore, a low-IF frequency for FM broadcasts withinthe United States would be an IF frequency equal to or below about 600kHz. It is further noted that for spectrums with non-uniform channelspacings, a low-IF frequency would be equal to or below about threesteps in the channel tuning resolution of the receiver circuitry. Forexample, if the receiver circuitry were configured to tune channels thatare at least about 100 kHz apart, a low-IF frequency would be equal toor below about 300 kHz. As noted above, the IF frequency may be fixed ata particular frequency or may vary within a low-IF range of frequencies,depending upon the LO generation circuitry 130 utilized and how it iscontrolled.

It is further noted that the architecture of the present invention canbe utilized for receiving signals in a wide variety of signal bands,including AM audio broadcasts, FM audio broadcasts, television audiobroadcasts, weather channels, and other desired broadcasts. Thefollowing table provides example frequencies and uses for variousbroadcast bands that can be received by the integrated terrestrialbroadcast receiver of the present invention.

TABLE 1 EXAMPLE FREQUENCY BANDS AND USES FREQUENCY USES/SERVICES 150-535kHz European LW radio broadcast 9 kHz spacing 535-1700 kHz MW/AM radiobroadcast US uses 10 kHz spacing European uses 9 kHz spacing 1.7-30SW/HF international radio broadcasting 46-49 Cordless phones and ‘babymonitors’, remote control 59.75 (2) US TV Channels 2-6 (VHF_L) 65.75 (3)6 MHz channels at 54, 60, 66, 76, 82 71.75 (4) Audio carrier is at 5.75MHz (FM MTS) 81.75 (5) 87.75 (6) 47-54 (E2) European TV 54-61 (E3) 7 MHzchannels, FM sound 61-68 (E4) Band I: E2-E4 174-181 (E5) Band III:E5-E12 181-188 (E6) 188-195 (E7) 195-202 (E8) 202-209 (E9) 209-216 (E10)216-223 (E11) 223-230 (E12) 76-91 Japan FM broadcast band 87.9-108US/Europe FM broadcast band 200 kHz spacing (US) 100 kHz spacing(Europe) 162.550 (WX1) US Weather Band 162.400 (WX2) 7 channels, 25 kHzspacing 162.475 (WX3) SAME: Specific Area Message Encoding 162.425 (WX4)162.450 (WX5) 162.500 (WX6) 162.525 (WX7) 179.75 (7) US TV Channels 7-13(VHF_High) 6 MHz channels at 174, 180, 186, 192, 198, 204, 210 215.75(13) FM Sound at 5.75 MHz 182.5 (F5) French TV F5-F10 Band III 8 MHzchannels 224.5 (F10) Vision at 176, 184, 192, 200, 208, 216 MHz AM soundat +6.5 MHz 470-478 (21) Band IV - TV Broadcasting Band V - TVBroadcasting 854-862 (69) 6 MHz channels from 470 to 862 MHz UK System I(PAL): Offsets of +/− 25 kHz may be used to alleviate co- channelinterference AM Vision carrier at +1.25 (Lower Sideband vestigial) FMWSound carrier at +7.25 Nicam digital sound at +7.802 French System L(Secam): Offsets of +/− 37.5 kHz may be used. AM Vision carrier at +1.25(inverted video) AM Sound carrier at +7.75 Nicam digital sound at +7.55470-476 (14) US TV Channels 14-69 6 MHz channels 819-825 (69) Soundcarrier is at 5.75 MHz (FM MTS) 14-20 shared with law enforcement

FIG. 1B is a more detailed block diagram for the low-IF circuitry 106and the DSP circuitry 108 of FIG. 1A where the receiver circuitry isutilized for an integrated FM terrestrial broadcast receiver. Moreparticularly, in the embodiment 150 of FIG. 1B, the low-IF circuitry 106includes variable gain amplifiers (VGAs) 152 and 154 that receive thereal (I) and imaginary (Q) signals 116 that have been mixed down to alow-IF frequency by mixer 104. The output of VGA 152 is then convertedfrom low-If to the digital domain using band-pass ADC 158. Similarly,the output of VGA 154 is converted from low-IF to the digital domainusing band-pass ADC 156. Together, the ADCs 156 and 158 produce the real(I) and imaginary (Q) digital output signals 120. The DSP circuitry 108conducts digital processing in the digital domain to further tune thetarget channel. More particularly, the low-IF DSP circuitry 108 utilizesa channel selection filter, as represented by the channel filter block162, to further tune the target channel. As indicated above, the DSPcircuitry 108 can also implement digital processing to provide FMdemodulation of the tuned digital signals, as represented by FM DEMODblock 166, and can implement stereo decoding, such as MPX decoding, asrepresented by stereo decoder block 164. In addition, embodiment 150 cantune and decode RDS (Radio Data System) and/or RBDS (radio broadcastdata System) information utilizing in part the RDS/RBDS decoder 168within the DSP circuitry 108. The output signals from the low-IF DSPcircuitry 108 are left (L) and right (R) digital audio signals 122. Ifdesired, integrated digital-to-analog converters (DACs), such as DACs170 and 172, can be utilized to convert these digital audio signals toleft (L) and right (R) analog audio signals 212. It is also noted that,if desired, ADCs 156 and 158 could also be implemented as complexbandpass ADCs, as real low-pass ADCs, or as any other desired ADCarchitecture.

As indicated above, the architectures of the present invention areadvantageous for small, low-cost portable devices and are particularlyadvantageous for such devices that need to receive terrestrial audiobroadcasts, such as FM broadcasts. In particular, the LO generationcircuitry 130, the mixer 104, the low-IF conversion circuitry 106 andthe DSP circuitry 108 are preferably all integrated on the sameintegrated circuit. In addition, the LNA 102 and other desired circuitrycan also be integrated into the same integrated circuit. This integratedcircuit can be made, for example, using a CMOS process, a BiCMOSprocess, or any other desired process or combination of processes. Inthis way, for example, a single integrated circuit can receive aterrestrial broadcast signal spectrum and output digital or analog audiosignals related to a tuned terrestrial broadcast channel. Preferably,the integrated circuit is a CMOS integrated circuit, and preferably anintegrated CMOS terrestrial broadcast receiver of the present inventionis configured in a 4×4 mm 24-pin micro lead-frame (MLP) package toprovide advantageous cost, size and performance features for small,portable devices, such as cellular handsets, portable audio devices, MP3players, portable computing devices, and other small, portable devices.

Power consumption is an additional concern with such small, portabledevices. The integrated receiver architecture of the present inventionadvantageously provides for reduced power consumption and allows for theuse of power supplies with different ranges to power the integratedreceiver. In particular, the present invention allows for low currentconsumption of less than or equal to 30 mA (milli-Amps) of supplycurrent. In addition, the level of integration provided by the presentinvention allows for a small package size and reduced number of externalcomponents that is less than or equal to about six (6) externalcomponents.

FIG. 1C is a block diagram of one example embodiment 175 for anintegrated terrestrial broadcast receiver 196. In the embodimentdepicted, the integrated receiver 196 includes an AM antenna and an FMantenna. The FM antenna 111 provides a differential FM input signal,which is represented by signals FMIP (FM input positive) and FMIN (FMinput negative), to a first low noise amplifier (LNA) 102A. The FMINnode is coupled to ground 113. The AM antenna 115 provides adifferential AM input signal, which is represented by signals AMIP (AMinput positive) and AMIN (AM input negative), to a second low noiseamplifier (LNA) 102B. The AMIN node is coupled to ground 113. The AMantenna 115, as depicted, is a ferrite bar antenna, and the AM receptioncan be tuned using an on-chip variable capacitor circuit 198. Theconnection between the on-chip variable capacitor circuit 198 and the AMantenna 115 is represented by the AMCAP signal. It is also noted thatthe FM antenna reception can also be tuned with an on-chip variablecapacitor circuit, if desired. With respect to the power supply for theintegrate receiver 196, an integrated supply regulator (LDO) block 185can be provided to help regulate the on-chip power.

As with FIG. 1A, the outputs of the LNAs 102A and 102B are processed bymixer 104 to generate real (I) and an imaginary (Q) signals. Thesesignals are then processed by a programmable gain amplifier (PGA) 176,which is controlled by the automatic gain control (AGC) block 180. Theoutput signals from the PGA 176 are then converted to digital I and Qvalues with I-path ADC 158 and Q-path ADC 156. DSP circuitry 108 thenprocesses the digital I and Q values to produce left (L) and right (R)digital audio output signals that can be provided to the digital audioblock 194. In addition, these left (L) and right (R) digital audiooutput signals can be processed with additional circuitry, asrepresented by digital-to-analog conversion (DAC) circuits 170 and 172,to produce left (LOUT) and right (ROUT) analog output signals. Theseanalog output signals can then be output to listening devices, such asheadphones. Amplifier 178 and speaker outputs 177A and 177B, forexample, can represent headphones for listening to the analog audiooutput signals. As described above with respect to FIG. 1B, the DSPcircuitry 108 can provide a variety of processing features, includingdigital filtering, FM and AM demodulation (DEMOD) and stereo/audiodecoding, such as MPX decoding. Low-IF block 186 includes additionalcircuitry utilized to control the operation of the DSP circuitry 108 inprocessing the digital I/Q signals.

A digital control interface 190 can also be provided within integratedreceiver 196 to communicate with external devices, such as controller192. As depicted, the digital communication interface includes apower-down (PDN_) input signal, reset (RST_) input signal, abi-directional serial data input/output (SDIO) signal, a serial clockinput (SCLK) signal, and a serial interface enable (SEN) input signal.As part of the digital interface, digital audio block 194 can alsooutput digital audio signals to external devices, such as controller192. As depicted, this communication is provided through one or moregeneral programmable input/output (GPIO) signals. The GPIO signalsrepresent pins on the integrated receiver 196 that can be userprogrammed to perform a variety of functions, as desired, depending uponthe functionality desired by the user. In addition, a wide variety ofcontrol and/or data information can be provided through the interface190 to and from external devices, such as controller 192. For example, aRDS/RBDS block 187 can report relevant RDS/RBDS data through the controlinterface 190. And a receive strength quality indicator block (RSQI) 188can analyze the receive signal and report data concerning the strengthof that signal through the control interface 190. It is noted that othercommunication interfaces could be used, if desired, including serial orparallel interfaces that use synchronous or asynchronous communicationprotocols.

Looking back to the mixer 104 of FIG. 1C, LO mixing signals are receivedby mixer 104 from a phase shift block (0/90) 132 that produces twomixing signals that are 90 degrees out of phase with each other. Thephase shift block 132 receives an oscillation signal from frequencysynthesizer (FREQ SYNTH) 182. Frequency synthesizer 182 receives areference frequency from reference frequency (REF) block 183 and acontrol signal from automatic frequency control (AFC) block 181. Anexternal crystal oscillator 184, operating, for example, at 32.768 kHz,provides a fixed reference clock signal to the reference frequency (REF)block 183 through connections XTAL1 and XTAL2. The AFC block 181 canreceive tuning error signal from the receive path circuitry within theintegrate receiver 196 and provide a correction control signal to thefrequency synthesizer 182. The use of such an error correction signal isdiscussed in further detail below.

FIGS. 2A, 2B, 3A and 3B will now be discussed. These figures provideadditional embodiments for receivers according to the present inventionthat utilize ratiometric clock systems for mixing circuitry and digitalcircuitry located on the same integrated circuit. The generated clocksignals are deemed ratiometric because the are all divisors or multiplesof at least one common clock signal. As discussed below, suchratiometric clock signals can be generated by first producing a baseoscillation signal that is then utilized to generate a plurality ofdependent clock signals through dividers or multipliers, such that theclock signals are all ratiometric with respect to each other.

FIG. 2A is a block diagram for an embodiment 200 of an integratedterrestrial broadcast receiver that utilizes a frequency synthesizer 209and ratiometric clock signals to provide LO mixing signals (f_(LO)) 118and a digital clock signal (f_(DIG)) 205 for the receiver circuitry. Aswith FIG. 1A, an RF input signal spectrum (f_(RF)) 112 is received by alow noise amplifier (LNA) 102 and processed by mixer 104 to generatereal (I) and imaginary (Q) signals 116. Low-IF conversion circuitry 106and DSP circuitry 108 processes these signals to produce left (L) andright (R) digital audio output signals 122. In addition, as shown inFIG. 1B, these left (L) and right (R) digital audio output signals 122can be processed with additional circuitry, as represented bydigital-to-analog conversion (DAC) circuits 170 and 172, to produce left(L) and right (R) analog output signals 212.

As further depicted in embodiment 200 of FIG. 2A, a phase shift block132 can be utilized, and this phase shift block 132 can be adivide-by-two block that produces two mixing signals 118 that are 90degrees out of phase with each other. The use of two mixing signals 90degrees out of phase is the typical technique for generating mixingsignals for mixers, such as mixer 104, to produce real (I) and imaginary(Q) signals, such as signals 116. If desired, phase shift block 132 mayalso be a divide-by-three block that produces two mixing signals thatare 120 degrees out of phase with each other. Depending upon theimplementation of the phase shift block 132, the processing provided bythe low-IF conversion circuitry 106 and the DSP circuitry 108 willchange accordingly. It is also noted that more generally block 132represents quadrature generation circuitry that can be implemented in anumber of different ways to achieve mixing signals 118 for the mixer104. In addition, if desired, the function of block 132 could beincluded within other blocks represented in FIG. 2A and FIGS. 3A-3B.

In the embodiment 200 depicted, the LO generation circuitry includes afrequency synthesizer 209, a divide-by-X block (÷X) 204, and quadraturegeneration circuitry or phase shift block 132. Phase shift block 132provides phase shifted LO mixing signals 118 to mixer 104. The frequencysynthesizer 209 generates an output signal (f_(OSC)) 252 that is at adesired frequency. The frequency synthesizer-209 can be implemented in avariety of ways, including the use of a phase locked loop (PLL), afrequency locked loop (FLL) or some other desired oscillation generationcircuitry. The frequency of the output signal (f_(OSC)) 252 isdetermined by control circuitry that utilizes a target channel inputsignal (TARGET CHANNEL) 222 to select the desired output frequency. Asdiscussed further below, the frequency of this target channel signal 222can be correlated to an integer (N) that is selected based upon thedesired channel. The frequency synthesizer 209 also utilizes an inputreference frequency (F_(REF)) 206 in generating an output signal(f_(OSC)) 252 at the desired frequency. The output signal (f_(OSC)) 252is then passed through the divide-by-X block (÷X) 204 to generate anoutput signal 117 that is used to generate the desired LO mixing signals(f_(LO)) 118 for the mixer 104. If desired, and as discussed in moredetail below, a band selection signal (BAND SELECTION) 207 can beutilized and can be applied to divide-by-X block (÷X) 204. This bandselection signal 207 can be utilized to adjust the tuning band for thereceiver 200. For example, the tuning band could be adjusted from the FMbroadcast band to the AM broadcast band. In this way, a single receivercan be used to tune channels within multiple broadcast bands.

Advantageously, the output signal (f_(OSC)) 252 can also be used toproduce the digital clock signal (f_(DIG)) 205 utilized by digitalcircuitry within the low-IF conversion circuitry 106, the DSP circuitry108, and the DACs 170 and 172. In this way, the digital clock signal(f_(DIG)) 205, other clock signals based upon the digital clock signal(f_(DIG)) 205, the LO mixing signals 118, the output signal (f_(OSC))252, and intervening clock nodes are all at frequencies that aredivisors or multiples of each other or of a common base clock signalthereby making the clock signals ratiometric. To produce the digitalclock signal (f_(DIG)) 205, the output signal (f_(OSC)) 252 is passedthrough a divide-by-Y block (÷Y) 202. By using the output signal(f_(OSC)) 252 to generate both the LO mixing signals 118 for the mixer104 and the digital clock signal (f_(DIG)) 205, these two resultingsignals become ratiometric, thereby tending to limit potentialinterference between the two signals because digital harmonics of thesesignals will tend to fall on the frequency of the oscillation signal(f_(OSC)) 252. Previous systems typically used an external referenceclock to drive a digital clock signal on a separate integrated circuitfrom the mixing circuitry. If such systems then attempted to integratethe mixer and digital circuitry into the same integrated circuit,performance-degrading interference would typically be generated. Incontrast, the ratiometric clock feature of the present invention reducesundesirable interference and allows for improved performance of anintegrated receiver.

FIG. 2B is a block diagram for the basic structure of a ratiometricclock system 250 and sets forth the basic elements for the ratiometricclock of the present invention. An input oscillation signal (f_(OSC))252 is received by system 250. This oscillation signal (f_(OSC)) 252 canbe generated using a wide variety of different circuits. For example, aPLL could be utilized to provide the oscillation signal (f_(OSC)) 252that is used to generate LO mixing signals 118 and the digital clocksignal (f_(DIG)) 205. In FIG. 3A, which is discussed below, a voltagecontrolled oscillator (VCO) 314 is used to generate an oscillationsignal (f_(VCO)) 315 that is used to generate LO mixing signals 118 andthe digital clock signal (f_(DIG)) 205. The VCO 314 can be controlled aspart of a PLL, for example, or through a frequency locked loop controlalgorithm implemented within the tuning control circuitry 312. In short,the ratiometric clock of the present invention can be utilized with awide range of circuits that can produce the starting oscillation signalfrom which a plurality of other ratiometric clock signals are generated.

Looking back to the example of FIG. 2B, it is seen that a first andsecond divider circuits are used to generate two ratiometric clocksignals. In particular, as depicted, divide-by-X block (÷X) 204 receivesthe input oscillation signal (f_(OSC)) 252 and outputs signal 117. Thisoutput signal 117 is processed by quadrature generation (QUAD GEN)circuitry 132 to generate the two LO mixing signals (f_(LO)) 118 thatcan be used by mixer 104. Divide-by-Y block (÷Y) 202 receives the inputoscillation signal (f_(OSC)) 252 and outputs a digital clock signal(f_(DIG)) 205 that can be used to generate digital clock signals used byintegrated digital circuitry, such as digital circuitry within thelow-IF conversion circuitry 106 and DSP circuitry 108. It is noted thatother ratiometric clock signals could be generated if desired and thatthe ratiometric clocks generated could be utilized for other purposes ifdesired. And it is noted that the mixer circuitry and the digitalcircuitry that use these ratiometric clock signals, along with theratiometric clock system 250, would preferably be integrated into thesame integrated circuit.

In operation, as stated above, the ratiometric clock feature of thepresent invention helps to reduce undesired interference because themixing signals and the digital clock signals are divisors or multiplesof each other or of a common base clock signal. Along with the integer Nrelated to the target channel signal 222, the divide values X and Yprovide programmable control of the clock signals being utilized. Forexample, the following equations can be used to represent the circuitrypresented in FIG. 3A, which is discussed in more detail below, and theratiometric values for the oscillation output signal (f_(OSC)) 252, thedigital clock signal (f_(DIG)) 205, and the LO mixing signals (f_(LO))118 (assuming a divide-by-two quadrature generator is utilized), whichare all based upon the reference frequency (f_(REF)) 206.f _(VCO)=(f _(REF) /R)·Nf _(signal 117) =f _(VCO) /X=(f _(REF) ·N)/(R·X)f _(LO) =f _(signal 117)/2=(f _(REF) ·N)/(2·R·X)f _(DIG) =f _(VCO) /Y=(f _(REF) ·N)/(R·Y)f _(VCO) =f _(LO)(2·X)=f _(DIG) ·YThe values of N, R, X and Y can then be selected and controlled toachieve the desired frequencies for these signals. And the selectioncriteria for the values of N, R, X and Y can be implemented as desired.For example, these values can be selected according to an on-chiplook-up table or could be set through a user-configurable register. Asshown in FIG. 3A, an error signal (ERROR) 322 may also be generated, forexample, using the DSP circuitry 108, that identifies errors in tuningthe received signal. This error signal can then be used to modify the Nvalue in order to reduce frequency error essentially to zero when tuninga received signal.

As an example for an FM spectrum, the reference frequency (f_(REF)) 206can be selected to be 32.768 kHz. The low-IF target frequency can beselected to be about 200 KHz. X can be selected to be 12. Y can beselected to be 100. N and R can be selected to vary depending upon theFM channel to be tuned. For example, for a desired FM channel to betuned that is centered at about 100 MHz, N can be selected to be 73096with R considered nominally to be equal to 1. With these numbersselected, the oscillation signal (f_(OSC)) 252 would be 2.395 GHz. Thedigital clock signal (f_(DIG)) 205 would be 23.95 MHz. The output signal117 would be 199.6 MHz. And the LO mixing signals (f_(LO)) 118 to mixer104 would be 99.8 MHz. The mixer 104 would then mix the input signalspectrum 112 (f_(RF)) with the mixing signals 118 from phase block 132to mix the desired FM channel at 100 MHz to a low-IF target frequency ofabout 200 kHz (i.e., 100.0 MHz 99.8 MHz component ends up at about 200kHz). The appropriate N value for each channel with the FM broadcastspectrum could then be similarly selected such that the mixer 104 mixesthe desired channel down to the target IF frequency. It is noted thatthe values for X and Y could also be modified, if desired. And it isnoted that the target IF frequency could be a variable frequency, forexample, if discrete tuning steps were used for the LO generationcircuitry.

In addition, as indicated above, the divide-by-X block (÷X) can alsoreceive the band selection signal (BAND SELECTION) 207. This signal canbe used to select the frequency band within which the receiver is tuningchannels. For example, the oscillation output signal (f_(OSC)) 252 canbe a signal at about 2-3 GHz or greater, and the band selection signal(BAND SELECTION) 207 can be used to select what values are used for X,thereby determining the tuning range for the receiver. This technique isuseful because many oscillators have a good operating range from minimumto maximum frequency that differ by a factor of about 1.3. Thus, the FMspectrum from 88.1 to 107.9 can be tuned using a single on-chiposcillator because this correlates to oscillation output signal(f_(OSC)) 252 of about 2.114 GHz to 2.590 GHz, assuming the value of 12for X, and this range is within a factor of 1.3 from minimum to maximumfrequencies. However, if additional broadcast spectrums were desired tobe tuned, this single on-chip oscillator would have to operate outsideof its good operating range, unless other factors were modified. Withthe architecture described above, the values for X (and N) can beadjusted to move the resulting tuning range into the desired frequencyband while still using the same on-chip oscillator.

FIG. 3A is a block diagram of an alternative embodiment 300 for anintegrated terrestrial broadcast receiver that utilizes tuning controlcircuitry 312 and a ratiometric clock system to provide an LO mixingsignals (f_(LO)) 118 and a digital clock signal (f_(DIG)) 205 for thereceiver circuitry. As with FIGS. 1 and 2A, an RF input signal spectrum(f_(RF)) 112 is received by a low noise amplifier (LNA) 102 andprocessed by mixer 104 to generate real (I) and an imaginary (Q) signals116. Low-IF conversion circuitry 106 and DSP circuitry 108 process thesesignals to produce left (L) and right (R) digital audio output signals122. In addition, as shown in FIG. 2A, these left (L) and right (R)digital audio output signals 122 can be processed with additionalcircuitry, as represented by digital-to-analog conversion (DAC) circuits170 and 172, to produce left (L) and right (R) analog output signals212. Also, as in FIG. 2A, the LO input signal (f_(LO)) 118 and thedigital clock signal (f_(DIG)) 205 can be generated as ratiometric clocksignals using divide-by-X block (÷X) 204 and divide-by-Y block (÷Y) 202.And a band selection signal (BAND SELECTION) 207 can also be applied todivide-by-X block (÷X) 204, if desired. In addition, a quadraturegenerator or phase shift block 132 provides phase shifted mixing signals118 to mixer 104.

As depicted in more detail in FIG. 3A, dotted line 304 represents thedigital circuitry within a single integrated circuit, such as digitalcircuitry within the low-IF conversion circuitry 106, DSP circuitry 108and the DACs 170 and 172. In particular, analog-to-digital converter(ADC) 156 and ADC 158 represent the analog-to-digital conversioncircuitry that produces the real (I) and imaginary (Q) digital signals120. ADC 156 and ADC 158 utilize a sampling clock signal based upon thedigital clock signal (f_(DIG)) 205. Similarly, the circuitry within theDSP circuitry 108 utilizes clock signals based upon the digital clocksignal (f_(DIG)) 205. In contrast with the embodiment 200 of FIG. 2A, inthe embodiment 300 of FIG. 3A, it is shown that the digital clock signal(f_(DIG)) 205 can be selected through a multiplexer (MUX) 328 to be aratiometric clock signal 329 or an external reference clock signal(f_(REF) _(—) _(FIXED)) 320. Although it is desirable for theratiometric clock signal 329 to be utilized in order to reduceperformance degrading interference, an external reference clock signal,such as clock signal (f_(REF) _(—) _(FIXED)) 320 could be used, ifdesired. In addition, if desired, rather than being selected through MUX328, the clock signal (f_(REF) _(—) _(FIXED)) 320 could be used as aseparate clock source in addition to the digital clock signal (f_(DIG))205 for digital circuitry 304. For example, a switch 321 could be usedto supply the clock signal (f_(REF) _(—) _(FIXED)) 320 directly to thedigital circuitry 304 so that both the clock signal (f_(REF) _(—)_(FIXED)) 320 and the ratiometric clock signal 329 could be utilized bythe digital circuitry 304. Such an embodiment is also described in moredetail with respect to FIG. 3B below. It is further noted that thedigital clock signal (f_(DIG)) 205 from the MUX 328 and the referenceclock signal (f_(REF) _(—) _(FIXED)) 320 could be passed throughadditional dividers, multipliers or other clock generation circuitsbefore being utilized as clock signals for the digital circuitry 304within the low-IF conversion circuitry 106 and the DSP circuitry 108.And one or more different clock signals could be generated for use withthe different circuit blocks within the digital circuitry 304.

The tuning control circuitry 312 of FIG. 3A controls a voltagecontrolled oscillator (VCO) 314, which in turn generates an oscillationsignal (f_(VCO)) 315 that is used to generate the ratiometric clocksignals. The tuning control circuitry 312 receives a target channelsignal (TARGET CHANNEL) 222, which represents the desired channel to betuned, receives the oscillation signal 315 from the VCO 314 as afeedback signal, and receives a reference frequency signal (f_(REF))206. As discussed above, the target channel signal 222 can be correlatedto an integer (N) that is selected based upon the desired channel.Divider blocks, represented by divide-by-N block (÷N) 316 anddivide-by-R block (÷R) 318, have values that are selected based upon thetarget channel signal (TARGET CHANNEL) 222 to control the coarse andfine tune signals 317 and 319. More particularly, the value for Ncorresponds to the desired target channel, assuming R has a nominalvalue of 1. In the embodiment depicted, the fine tune signal (FINE TUNE)319 and the coarse tune signal (COARSE TUNE) 317 are 10-bit controlsignals. It is noted that the coarse and fine tune signals 317 and 319can be signals of any desired bit size, can be of different sizes, andcan be variable or analog signals, if desired. Other control signalscould also be utilized, as desired, depending upon the VCO circuitryutilized for VCO 314. It is further noted that the VCO circuitryrepresented by block 314 can be implemented using a number of differentoscillator circuits. Example oscillator circuitry that can be utilizedis described in U.S. Pat. No. 6,388,536, which is entitled “METHOD ANDAPPARATUS FOR PROVIDING COARSE AND FINE TUNING CONTROL FOR SYNTHESIZINGHIGH-FREQUENCY SIGNALS FOR WIRELESS COMMUNICATIONS” and which is herebyincorporated by reference in its entirety.

It is also noted that the VCO 314 may preferably have an outputfrequency equal to or above about 2.3 GHz in order to reduceinterference with other services, such as cell phone operationalfrequencies. This relatively high output frequency also facilitates anefficient, small integrated circuit where LC tank oscillation circuitsare utilized because the LC tank elements can be made relatively small.In particular, with output frequencies for the VCO 314 in this range ofbeing equal to or above about 2.3 GHz, the one or more inductors thatwould be needed for an LC tank implementation of the VCO 314 can beintegrated into the integrated circuit or included with the devicepackage.

In operation, the tuning control circuitry 312 first receives the targetchannel signal (TARGET CHANNEL) 222 indicating the channel to be tunedwithin the frequency spectrum of the input signal spectrum (f_(RF)) 112.The tuning control circuitry 312 places the fine tune signal (FINE TUNE)319 at a nominal or initial setting, and tuning control circuitry 312then outputs a coarse tune signal (COARSE TUNE) 317 to provide coarsetuning of the VCO 314. The tuning control circuitry 312 then adjusts thefine tune signal (FINE TUNE) 319 to fine tune and lock the VCO 314 tothe desired oscillation output signal 315. A feedback signal fromoscillation signal 315 is then used to control the tuning of the outputfrom the VCO 314. In addition, an error signal (ERROR) 322 can also beutilized to help accomplish this tuning. The error signal (ERROR) 322can represent tuning errors in the received signal, and the tuningcontrol circuitry 312 can use this error signal to automatically adjustthe output frequency of the VCO 314 to correct for these tuning errors.Thus, both the feedback signal from the output signal 315 of the VCO 314and an additional error signal (ERROR) 322 can be utilized by the tuningcontrol circuitry 312 for frequency control.

When the oscillation signal 315 is changed in order to tune a particulardesired channel, the digital clock signal (f_(DIG)) 205 will also changein a ratiometric fashion depending upon the selection of the values forX and Y in blocks 204 and 202, respectively. Similarly, this change inthe digital clock signal (f_(DIG)) 205 also happens with changes to theoutput signal (f_(OSC)) 252 of FIG. 2A. Because of this change in thedigital clock signal (f_(DIG)) 205, as shown in FIG. 3A, an LO jumpsignal (JUMP) 326 can be output by the tuning control circuitry 312 toindicate that a change in the oscillation signal 315 has occurred. Usingthis LO jump signal (JUMP) 326, the digital circuitry 304 can utilizecompensation routines, if desired, to adjust operation for theratiometric change in the digital clock signal (f_(DIG)) 205.

As described above, the X and Y divider blocks in FIGS. 2A, 2B, 3A and3B can be changed by program or algorithm control, as desired, toachieve the oscillation frequencies and the ratiometric ratios desired.For example, it is desirable that a change in the oscillation signals252 and 315 of FIGS. 2A, 3A and 3B correlate to less than a 1% change inthe value of the digital clock signal (f_(DIG)) 205. The values for Xand Y in blocks 204 and 202, therefore, can be selected accordingly. Itis noted that an integrated on-chip microcontroller can be utilized toprovide control of the dividers and other receiver operation parameters,if desired. And this microcontroller can also be used to implement someor all of the digital processing done by the DSP circuitry 108.

For additional control, as indicated above, the tuning control circuitry312 can receive an error signal (ERROR) 322 from the digital circuitry304. This error signal (ERROR) 322 from the digital circuitry 304represents an error signal correlating to noise or interference detectedin the receive path due to errors in the tuning of the input signalspectrum (f_(RF)) 112 to the proper channel. The tuning controlcircuitry 312 can utilize this error signal (ERROR) 322 to adjust the Nvalue within block 316 so as to more finally tune the received signal.Also, additional control signals, as represented by element 325, can beprovided from the DSP circuitry 108 to the LNA 102, the low-IFconversion circuitry 106, or other receiver circuitry to provide controlfor those circuits.

FIG. 3B is a block diagram of an additional alternative embodiment 350for an integrated terrestrial broadcast receiver that utilizes aratiometric digital clock (f_(DIG)) 205 and an fixed external referenceclock (f_(REF) _(—) _(FIXED)) 320 for digital circuitry within theintegrated receiver. An RF input signal spectrum (f_(RF)) 112 isreceived by a low noise amplifier (LNA) 102 and processed by mixer 104to generate real (I) and an imaginary (Q) signals. The signals are thenprocessed with VGAs 152 and 154 and ADCs 158 and 156 to produce digitalsignals. These digital signals are then provided to an I-path buffer(BUF) 354 and a Q-path buffer (BUF) 352 before being processed by theDSP 108 to generate digital left and right audio signals. The outputs ofthe DSP 108 are then provided to a left audio signal buffer (BUF) 356and a right audio signal buffer (BUF) 358. The outputs of these buffers356 and 358 can provide the left (L) and right (R) digital audio signals122. The outputs of these buffers 356 and 358 can also be provided toDACs 170 and 172 to produce left (L) and right (R) analog audio signals212. The clock signals utilized in this embodiment 350 are described inmore detail below.

As with earlier embodiments, the LO input signal (f_(LO)) 118 and thedigital clock signal (f_(DIG)) 205 can be generated as ratiometric clocksignals using divide-by-X block (÷X) 204 and divide-by-Y block (÷Y) 202.The output of the divide-by-X block (÷X) 204 passes throughdivide-by-two (÷2) 132 to provide the two out-of-phase LO mixing signals118. A frequency synthesizer 182 generates the oscillation signal(f_(OSC)) 252 and is controlled by the automatic frequency control (AFC)block 181. The AFC block 181 receives an external reference signal(f_(REF)) 206, a channel selection (CHANNEL) signal 222, and a tuningcorrection error (ERROR) signal 322. These signals are discussed abovewith respect to FIG. 3A. In addition, it is noted that the externalreference signal (f_(REF)) 206 can be the same signal as the fixedexternal reference clock (F_(REF) _(—) _(FIXED)) 320 or can be generatedfrom the fixed external reference clock (f_(REF) _(—) _(FIXED)) 320, ifthis clock configuration is desired.

The clock signals for the digital circuitry within embodiment 350 areprovided using the digital clock signal (f_(DIG)) 205 and the fixedexternal reference clock (F_(REF) _(—) _(FIXED)) 320. The fixed externalreference clock (F_(REF) _(—) _(FIXED)) 320 can be generated, ifdesired, by a crystal oscillator (XTAL OSC) 374 operating, for example,at 12.288 MHz. The DSP circuitry 108 can be clocked using the digitalclock signal (f_(DIG)) 205, which is ratiometric with respect to theoscillation signal (f_(OSC)) 252, as discussed above. Again, by using aratiometric clock signal to clock the DSP circuitry 108, interference(as represented by arrow 372) with the mixing circuitry 104 and otheranalog circuitry on the integrated circuit is reduced. Rather than beclocked using the digital clock signal (f_(DIG)) 205, the digital audiooutput circuitry 362 and the external CODEC 364 are clocked using thefixed external reference clock (f_(REF) _(—) _(FIXED)) 320. The ADCs andDACs 156, 158, 170 and 172 in this embodiment are also clocked using thefixed external reference clock (f_(REF) _(—) _(FIXED)) 320. Because theDSP 108 and the ADCs and DACs 156, 158, 170 and 172 are operating atdifferent clock frequencies, the buffers 352, 354, 356 and 358 can beused to buffer the data between the different data rates. These buffers352, 354, 356 and 358 can be, for example, dual port buffer memoriesthat have the ability to input data at one desired clock rate and outputdata at another desired clock rate.

This clocking architecture can provide advantages for receiverapplications where integrated circuits need to communicate at aspecified rate. Audio standards, for example, can require communicationsto provide audio data at a particular rate, such as 48,000 samples persecond (48 ks/s). In the embodiment of FIG. 3B, the digital audio outputcircuitry 362 would communicate the left (L) and right (R) digital audiosignals 122 to the external CODEC 364 at the specified rate through anexternal interface 370. So that the sample rates correlate to thespecified communication rates, the ADCs and DACs 156, 158, 170 and 172can also be clocked using the fixed external reference clock (f_(REF)_(—) _(FIXED)) 320. Although some interference may be generated usingthese non-ratiometric clock signals, the advantages of correlated samplerates make this architecture advantageous. It is noted that dotted line360 represents the boundary of the integrated circuit.

FIG. 4A is a block diagram of an embodiment 450 for an integratedterrestrial broadcast receiver that includes both AM broadcast receptionand FM broadcast reception. In the embodiment depicted, input FMbroadcast signals 112A are sent as differential signals to LNA 102A. Thedifferential output of LNA 102A is sent to mixer 104A, which uses LOmixing signals 118A from LO generation circuitry 130 to produce I and Qsignals 116A. These quadrature FM signals can then processed by the ADCand DSP circuitry integrated within the same integrated circuit. InputAM broadcast signals 112B are sent to LNA 102B and then to mixer 104B.Mixer 104B uses LO mixing signals 118B from LO generation circuitry 130to produce I and Q signals 116B. These quadrature AM signals can thenprocessed by the ADC and DSP circuitry integrated within the sameintegrated circuit. In operation, the LO generation circuitry 130 canreceive a band selection (BAND SELECTION) signal 207 that allows aselection of which broadcast band is to be processed by the receiver. Itis also noted that the LO generation circuitry 130, if desired, cangenerate a single set of mixing signals that can be used by both the FMmixer 104A and the AM mixer 104B, depending upon the selection made bythe band selection signal 207.

FIG. 4B is a block diagram of an embodiment 400 for a portable device402 that utilizes a low-IF integrated terrestrial broadcast receiver 100according to the present invention. As depicted, the portable deviceincludes a low-IF receiver integrated circuit 100 coupled to a channelselection interface circuitry 404 through connections 412 and to anaudio output interface circuitry 406 through connections 410. The audiooutput interface circuitry 406 is in turn coupled to listening device408 through connections 414. In such a portable environment, thelistening device 408 is often headphones that can be easily plugged intothe portable device 402. The embodiment 400 can also include one or moreantennas, such as an FM broadcast antenna 420 and an AM broadcastantenna 422. It is noted that a portable device as contemplated in thisembodiment is preferably a small portable device in that it has a volumeof about 70 cubic inches or less and has a weight of about 2 pounds orless. For example, as indicated above, the small, portable device 402could be a cellular phone, an MP3 player, a PC card for a portablecomputer, a USB connected device or any other small portable devicehaving an integrated terrestrial audio broadcast receiver. It is alsonoted that the audio output interface 406 can provide digital audiooutput signals, analog audio output signals, or both. And the interfacecircuitry 406 and 408 could be combined, if desired, such as would bethe case if a single serial or parallel interface were used to providethe communication interface for the portable device 402.

FIG. 5A is a block diagram for an embodiment 520 of an integratedterrestrial broadcast receiver that includes local oscillator (LO)control circuitry 500 for adding certain frequency control features. Aswith the embodiment 100 in FIG. 1A, an RF input signal spectrum (f_(RF))112 is received by a low noise amplifier (LNA) 102 and processed bymixer 104 to generate real (I) and an imaginary (Q) signals 116. Low-IFconversion circuitry 106 and DSP circuitry 108 processes these signalsto produce left (L) and right (R) digital audio output signals 122. Asdiscussed above with respect to FIG. 1A, it is again noted that other ordifferent output signals could be provided by the receiver, if desired.In addition, the LO mixing signals (f_(LO)) 118 are generated by LOgeneration circuitry 130, and these phase shifted mixing signals 118 areused by mixer 104, as discussed above.

LO control circuitry 500 is added in FIG. 5A to implement additionalfrequency control features. One such feature is a high-side versuslow-side LO signal injection selection feature as represented by block(HI/LO INJECTION) 510. Another feature is a programmable IF locationselection feature as represented by block (IF SELECTION) 512. Thesefrequency control features are discussed in more detail with respect toFIGS. 5B and 5C. The LO control circuitry 500 is coupled to the DSPcircuitry 108 through one or more signals 504 and to the LO generationcircuitry 130 through one or more signals 506.

FIG. 5B is a signal diagram for a high-side versus low-side LO signalinjection selection feature. In the example 550, a desired channel(f_(CH)) to be tuned is represented by signal arrow 554. A largerinterference signal (f_(IMH)) is represented by signal arrow 552. As iswell known, mixer 104 will mix the input RF signal spectrum (f_(RF)) 112to the intermediate frequency (f_(IF)) in accordance with the equationf_(RF)−f_(LO)=f_(IF) if low-side injection is utilized and in accordancewith the equation f_(IF)=f_(LO)−f_(RF) high-side injection is utilized.The designations f_(LOL) and f_(LOH) represent these two possible LOsignals for the low-side injection signal (f_(LOL)) 562 and high-sideinjection signal (f_(LOH)) 560, respectively. Many systems operate byimplementing either high-side injection or low-side injection and do notprovide the ability to switch between the two during operation. Somesystems have attempted to select between high-side and low-sideinjection during operation by assessing the level of noise or spurs inthe tuned target channel signal after it has been processed through thereceive path circuitry.

With the LO control circuitry 500 of the present invention, however,dynamic selection of high-side or low-side injection is implemented bymaking an assessment of image signal power within the spectrum beforethe selection of high-side or low-side injection is made and before thedesired channel itself has been processed and tuned. This selection canbe made, for example, using a selection algorithm that is configured todetermine whether high-side injection or low-side injection ispreferable based upon the image power at frequencies that are equal indistance from the LO frequencies as the desired channel. By tuning tothese frequencies and through signals 504 from the DSP circuitry 108,for example, the LO control circuitry can assess the signal power atfrequencies that could create significant performance-degrading images.In particular, the next adjacent upper image signal power and the nextadjacent lower image signal power can be assessed to determine whetheror not to use high-side or low-side injection. And this assessment canbe made at power-up across the entire spectrum, periodically across theentire spectrum, across a reduced spectrum that includes the desiredchannel to be tuned, each time a channel is tuned, or at any otherdesired time across any desired portion of the spectrum depending uponthe algorithm implemented.

Looking back to FIG. 5B, interference signal (f_(IMH)) 552 represents anupper image signal that is as far from the high-side LO injection signal(f_(LOH)) 560 as is the desired channel (f_(CH)) 554. If high-sideinjection were utilized, the mixer would use the high-side injection LOsignal (f_(LOH)) 560, and the interference signal (f_(IMH)) 552 would bemixed onto the intermediate frequency (f_(IF)) along with the desiredchannel (f_(CH)) 554. Thus, the use of high-side injection would createa large undesirable image. Similarly, the interference signal (f_(IML))553 represents a lower image signal that is as far from the low-side LOinjection signal (f_(LOL)) 562 as is the desired channel (f_(CH)) 554.If low-side injection were utilized, the mixer would use the low-sideinjection LO signal (f_(LOL)) 562, and the interference signal (f_(IML))553 would be mixed onto the intermediate frequency (f_(IF)) along withthe desired channel (f_(CH)) 554. Thus, the use of low-side injectionwould create an undesirable image, but the image would have a signalpower that was much less than the signal power of the image caused byusing high-side LO injection. By assessing the signal power of the upperimage frequency and lower image frequency, the LO control circuitry candetermine whether high-side injection or low-side injection should beused. In the example 550, therefore, low-side injection should be usedto avoid mixing the larger interference signal (f_(IMH)) 552 onto theintermediate frequency (f_(IF)). It is noted that the signal power atother frequencies, such as harmonics of the upper and lower imagefrequencies, could also be assessed, if desired, in determining whetherto make the dynamic selection of whether to use high-side injection orlow-side injections.

FIG. 5C is a signal diagram for a programmable IF location selectionfeature. In the example 570, a desired channel (f_(CH)) to be tuned isrepresented by signal arrow 554, and low-side injection is being used.The LO control circuitry 500 provides programmable selection of the LOsignal that will be used by mixer 104 to mix the input RF signalspectrum (f_(RF)) 112 to the intermediate frequency (f_(IF)) inaccordance with the equation f_(RF)−f_(LO)=f_(IF). As shown, twoselectable IF target frequencies are represented by a first IF targetfrequency (f_(IF1)) 580 and a second IF target frequency (f_(IF2)) 582.For a given desired channel (f_(CH)) 554 to be tuned LO signals,therefore, a first LO signal (f_(LO1)) 578 is used if the first IFtarget frequency (f_(IF1)) 580 has been selected. And the line 572represents the action of mixer 104 in mixing the desired channel(f_(CH)) 554 down to the first IF frequency (f_(IF1)) 580. Similarly, asecond LO signal (f_(LO2)) 576 is used if the second IF target frequency(f_(IF2)) 582 has been selected. And the line 574 represents the actionof mixer 104 in mixing the desired channel (f_(CH)) 554 down to thesecond IF frequency (f_(IF2)) 582.

The programmable selection for the LO signal, as shown in the embodiment520 of FIG. 5A, is provided through an IF selection signal (IF CODE) 502that is received by the LO control circuitry 500. This IF CODE 502 canbe based, for example, upon a user programmable on-chip register.Factors for choosing the desired target IF frequency can include thechannel width of the RF spectrum of interest or other environmentalconsiderations. For example, if the integrated terrestrial broadcastreceiver 520 were intended for use in a variety of countries, adifferent target IF frequency could be selected for each country. Thisselection could depend upon the nature of the broadcast spectrum in thatcountry, including the respective channel widths. It is noted that awide variety of mechanisms could be employed for providing programmablecontrol to the LO control circuitry 500 to select which IF frequency isto be utilized in operation.

Further modifications and alternative embodiments of this invention willbe apparent to those skilled in the art in view of this description. Itwill be recognized, therefore, that the present invention is not limitedby these example arrangements. Accordingly, this description is to beconstrued as illustrative only and is for the purpose of teaching thoseskilled in the art the manner of carrying out the invention. It is to beunderstood that the forms of the invention herein shown and describedare to be taken as the presently preferred embodiments. Various changesmay be made in the implementations and architectures. For example,equivalent elements may be substituted for those illustrated anddescribed herein, and certain features of the invention may be utilizedindependently of the use of other features, all as would be apparent toone skilled in the art after having the benefit of this description ofthe invention.

1. An integrated receiver, comprising: a mixer coupled to receive an RFsignal spectrum and a mixing signal as inputs and having a mixed signalas an output, the RF input signal spectrum comprising a plurality ofchannels; local oscillator (LO) generation circuitry coupled to receivea channel selection signal as an input and configured to provide anoscillation signal, the oscillation signal being dependent upon thechannel selection signal and being used to generate the mixing signalfor the mixer; conversion circuitry coupled to receive the mixed signalfrom the mixer and configured to output a digital signal;digital-signal-processor (DSP) circuitry coupled to receive the digitalsignal from the conversion circuitry and configured to output a digitalaudio signal, the DSP circuitry being configured to be clocked inoperation using a digital clock signal; and a ratiometric clock systemconfigured to generate the mixing signal and the digital clock signalfrom the oscillation signal so that the mixing signal and the digitalclock signal have a common base clock signal; wherein the mixer, the LOgeneration circuitry, the conversion circuitry, and the DSP circuitryare integrated within a single integrated circuit.
 2. The integratedreceiver of claim 1, wherein the conversion circuitry is also configuredto be clocked in operation using the digital clock signal.
 3. Theintegrated receiver of claim 1, wherein the conversion circuitry isconfigured to be clocked in operation using a reference clock signalprovided from a source external to the single integrated circuit.
 4. Theintegrated receiver of claim 3, further comprising digital outputcircuitry configured to be clocked in operation using the referenceclock signal.
 5. The integrated receiver of claim 3, further comprisingdata buffer circuitry coupled between the conversion circuitry and theDSP circuitry.
 6. The integrated receiver of claim 1, wherein the mixerhas a low-IF mixed signal as an output and the conversion circuitrycomprises low-If conversion circuitry.
 7. The integrated receiver ofclaim 6, wherein the RF input signal comprises an terrestrial audiobroadcast spectrum.
 8. The integrated receiver of claim 7, wherein theterrestrial audio broadcast spectrum comprises an FM signal spectrumcomprising a plurality of FM terrestrial broadcast channels.
 9. Theintegrated receiver of claim 1, further comprising a digital-to-analogconverter (DAC) coupled to receive the digital audio signal from the DSPcircuitry and configured to output an analog audio signal.
 10. Theintegrated receiver of claim 1, wherein the ratiometric clock systemcomprises a first divider coupled between the oscillation signal and themixing signal and a second divider coupled between the oscillationsignal and the digital clock signal.
 11. The integrated receiver ofclaim 10, wherein the RF input signal spectrum comprises an FM audiosignal spectrum comprising a plurality of FM broadcast channels.
 12. Theintegrated receiver of claim 10, wherein the LO generation circuitrycomprises voltage controlled oscillator circuitry.
 13. An integratedreceiver, comprising: a mixer coupled to receive an RF signal spectrumand a mixing signal as inputs and having a mixed signal as an output,the RF input signal spectrum comprising a plurality of channels; localoscillator (LO) generation circuitry coupled to receive a channelselection signal as an input and configured to provide an oscillationsignal, the oscillation signal being dependent upon the channelselection signal and being used to generate the mixing signal for themixer; conversion circuitry coupled to receive the mixed signal from themixer and configured to output a digital signal;digital-signal-processor (DSP) circuitry coupled to receive the digitalsignal from the conversion circuitry and configured to output a digitalaudio signal, the DSP circuitry being configured to utilize a digitalclock signal; and a ratiometric clock system configured to generate themixing signal and the digital clock signal from the oscillation signal;wherein the mixer, the LO generation circuitry, the conversioncircuitry, and the DSP circuitry are integrated within a singleintegrated circuit; wherein the ratiometric clock system comprises afirst divider coupled between the oscillation signal and the mixingsignal and a second divider coupled between the oscillation signal andthe digital clock signal; and further comprising a multiplexerconfigured to receive the digital clock signal as an input and anexternal reference clock signal as an input and configured to provide anoutput clock signal to the digital circuitry within the low-IFconversion circuitry and with the DSP circuitry.
 14. A ratiometric clocksystem for an integrated receiver, comprising: local oscillator (LO)generation circuitry coupled to receive a channel selection signal as aninput and configured to provide an oscillation signal, the oscillationsignal being dependent upon the channel selection signal; a firstdivider coupled to receive the oscillation signal, the first dividerproviding an output signal utilized to generate mixing signals for amixer integrated on an integrated circuit with the LO generationcircuitry; and a second divider coupled to receive the oscillationsignal, the second divider providing an output signal utilized togenerate clock signals used in operation to clock digital signalprocessing (DSP) circuitry integrated on the integrated circuit with theLO generation circuitry; wherein the mixing signals and the clocksignals have a common base clock signal.
 15. The ratiometric clocksystem of claim 14, wherein the channel selection signal indicates an FMchannel within an FM terrestrial broadcast spectrum to be tuned by theintegrated receiver.
 16. The ratiometric clock system of claim 14,wherein the output signal from the second divider is further utilized togenerate clock signals used in operation to clock analog-to-digitalconversion circuitry integrated on the integrated circuit with the LOgeneration circuitry.
 17. The ratiometric clock system of claim 14,wherein the LO generation circuitry comprises voltage controlledoscillator circuitry.
 18. The rationmetric clock system of claim 14,wherein the LO generation circuitry is further configured to output asignal identifying when a change is made to the oscillation signal. 19.A method for tuning channels within a signal spectrum, comprising:generating an oscillation signal, the oscillation signal being dependentupon a channel selection signal; creating a mixing signal and a digitalclock signal based upon the oscillation signal, the mixing signal andthe digital clock signal being ratiometric so that they have a commonbase clock signal; mixing an RF input signal spectrum having a pluralityof channels with the mixing signal to generate an output signal;converting the output signal to a digital signal; and processing thedigital signal to generate tuned digital output signals; wherein thedigital clock signal is utilized in operation to clock circuitry in theconverting step, in the processing step, or in both the converting andthe processing steps; and wherein the generating, creating, mixing,converting and processing steps are performed within a single integratedcircuit.
 20. The method of claim 19, wherein the mixing step generates alow-IF output signal.
 21. The method of claim 20, wherein the RF inputsignal comprises an RF terrestrial broadcast spectrum.
 22. The method ofclaim 21, wherein the RF terrestrial broadcast spectrum comprises an FMsignal spectrum comprising a plurality of FM terrestrial broadcastchannels.
 23. The method of claim 19, further comprising converting thedigital signal to an analog signal within the single integrated circuit.24. The method of claim 19, wherein the mixing step comprises utilizingtwo phase shifted mixing signals based upon the oscillation signal togenerate real and imaginary low-IF signals.
 25. The method of claim 24,wherein the converting step comprises utilizing an analog-to-digitalconverter (ADC) circuit to convert the real low-IF signal to a digitalsignal and utilizing an analog-to-digital converter (ADC) circuit toconvert the imaginary low-IF signal to a digital signal.
 26. The methodof claim 19, wherein the converting step utilizes a reference clocksignal from a source external to the integrated circuit.